1. Field of the Invention
The present invention relates to a phase locked loop (PLL) output clock stabilization circuit that allows the PLL circuit to output a PLL clock signal after the operation thereof has become stable (locked) and to supply the PLL clock signal to circuits, for example, logic circuits provided in the next stage.
2. Description of the Related Art
Conventional PLL circuit technologies are described in, for example, Japanese Patent application Kokai No. H11-69263 and Motorola Users Manual “On-chip Clock Synthesis (OCCS)” published in January 2001, specifically FIG. 6-3 on page 6-7 and section 6.8.1.3 “PLL Frequency Lock Detector” on page 6-9 in the manual.
FIG. 6 is a basic circuit block diagram of a conventional frequency counter. FIG. 7 is a timing chart showing the operation of the circuit in FIG. 6.
A PLL circuit takes a certain time to output a clock pll_clk having an expected frequency after it has received a source clock (clk) or a reference clock. Therefore, when a clock pll_clk generated by a PLL circuit is used, a waiting time is required to obtain a stable clock pll_clk having an expected frequency.
As described in the above-described references, for example, one of conventional methods for detecting that the PLL circuit has been stabilized is to count a PLL output clock pll_clk by using a counter and determine its stability from the count value. Another method is to take a PLL output clock pll_clk out from the large-scale integrated circuit (LSI) and determine by observing the waveform of the PLL output clock.
In the latter method, if the frequency of a PLL output clock pll_clk is observed in a consecutive period, it will be found that the frequency continues to match an expected frequency from a certain time point. Therefore, it can be determined that the PLL circuit has entered a stable state at that time point.
To measure frequency F using the frequency counter comprising a flip-flop (hereinafter, referred to as “FF”) 1 and a counter 2 as shown in FIG. 6, the number of pulses npulse of a clock pll_clk that arrives over a certain or fixed period of time tenable during which an enable signal “enable” of the FF 1 is high is counted by the counter 2 as shown in FIG. 7. Then, the frequency F is calculated by the following equation.F=1/T=npulse/tenableA PLL output clock stabilization circuit is also proposed so that logic circuits or other circuits in the next stage do not malfunction due to an unstable PLL output clock pll_clk generated before the PLL circuit is stabilized.
FIG. 8 is a circuit block diagram showing an example of a conventional PLL output clock stabilization circuit.
The PLL output clock stabilization circuit comprises a PLL circuit 3, a counter 4, a comparator 5, and a gate circuit 6. The PLL circuit 3 multiplies a source clock (clk) by a predetermined multiplication factor to output a PLL clock pll_clk. The counter 4 counts up with the source clock (clk) and is reset by a reset signal “reset.” The comparator 5 is connected to the output of the counter 4. The gate circuit 6 is connected to the output of the PLL circuit 3.
To use the output clock pll_clk of the PLL circuit 3, first the LSI is evaluated and a time required for its stable operation is measured externally. Next, based on this time, a fixed value with a certain margin is determined and set to the comparator 5 as the number of times K the circuit waits for stability. The number of pulses of the source clock (clk) is counted by the counter 4 and this counted number is input to the comparator 5. In the comparator 5, when the counted number reaches the number of times K the circuit waits for stability, it outputs an enable signal “enable” to open the gate circuit 6, by which the PLL clock pll_clk has been blocked. A stable PLL clock PLL_CLK is thereby output from the gate circuit 6 and supplied to logic circuits and other circuits in the next stage.
The conventional PLL output clock stabilization circuit shown in FIG. 8, however, has the following problems.
The PLL circuit 3 has the number of times K the circuit waits for stability, which fluctuates due to the variations of operation temperature and voltage, and element characteristics. Therefore, when the number of times K the circuit waits for stability is set to a fixed value as in the circuit in FIG. 8, the time from when the PLL circuit 3 is stabilized until it is actually used may be wasted or, contrarily, the PLL circuit 3 may be used before it is stabilized.